ASICs
The capacity converter HT133 is suitable for
converting the signals of capacitive sensors. The ASIC has been
developed for capacitive inclination and acceleration sensors. Minor
capacity variations can be detected and will be converted into a
digital or analogue output signal.
General Parameters:
Supply voltage:
5VDC
±10%
Power consumption: 7.5 mW
Temperature range: -40 ... +125°C
Sensor capacity: < 30pF
Maximum resolution: 0.2 fF
Output signal: Digital, parallel 11 bit + sign
Analogue
Converting rate: 20kHz
General Parameters:
Supply voltage: 5V ± 5
%
Temperature range: -40 ... +105°C
General Parameters:
Supply voltage: 5V ± 5
%
Power consumption (two active chanels): 30 mW
Temperature range: -25 ... +85°C
Sensor capacity: C1, C2 < 30pF
Output ANAOUT_x: 1 V...4 V (=VREF_x, when C1=C2)
Short
Product Description
The ICs have been designed for connection to
incremental position and angular measurement systems with
sine-shaped output signals with a 90° phase shift. They can be
operated at a large number of transducer systems working according
to the most varied measuring principles. With a maximum
interpolation rate of 1000, 500, 200, are capable to slit the input
signal period into up to 1000, 500, 200 segments. An internal
counter provides a counting value which can be output via a serial
interface. Furthermore there is the possibility to output the data
as a pair of square waves for processing externally.
The Interpolation IC AIP40 is suitable for
increasing the resolution of incremental position and angular
measuring systems with sine shaped output signals. The IC can be
used with the standard voltage
signals as well as current signals. Furthermore photo diode arrays
and sensor bridges can be
connected directly. An adjustable minimum edge distance at the
output and a programmable analogue
and digital hysteresis enables the use also in case of noisy input
signals.
The DANA23 (Digital Adaptive Neuro ASIC) neurochip
implements a universal neurocontroller. The chip contains a complete
feed-forward network with integrated weight storage. Furthermore,
there is also a modified backpropagation learning algorithm
integrated into the ASIC.
General Parameters:
Technology: 0,35 μ CMOS
Chip size: 35 mm2
Supply voltage: 3,3 V
Clock frequency: 33 MHz
Power consumption: 0,5 W
Package type: CQFP 208
Dimensions: 30,6 mm x 30,6 mm x 4,1 mm
Processing speed at 33MHz: 45MCUPS1
Main Features:
- Self-contained IP-Core integrating
general-lossless compression & decompression functions.
- VHDL description language, targeting FPGA & ASIC implementations.
- Enhanced compression ratio, compressing 30-50% more than market
solutions.
- Typical compression rates 2.5-3:1 in standard industry file-sets.
- Typical performance 25-50 Mbytes/s depending on the application
and designer's choice.
- Software Libraries for compression/decompression available in
ANSI-C and Intel x86 languages.
- FPGA Development Board implementing ELDC-II available on request.
- Maskable interrupt generation on End-of-Compression
(Decompression), as well as on error handling.
You
can find more information in the products pages. |
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